VERILOG HDL: A GUIDE TO DIGITAL DESIGN AND SYNTHESIS 2/E

Appropriate for all courses in digital IC or systemdesign using the Verilog Hardware Description Language(HDL). Fully updated for the latest versions of VerilogHDL, this complete reference progresses logically fromthe most fundamental Verilog concepts to today's mostadvanced digital design techniques. Written for bothexperienced students and newcomers, it offers broadcoverage of Verilog HDL from a practical designperspective. One step at a time, Samir Palnitkarintroduces students to gate, dataflow (RTL),behavioral, and switch level modeling; presents theProgramming Language Interface (PLI); describes leadinglogic synthesis methodologies; explains timing anddelay simulation; and introduces many other essentialtechniques for creating tomorrows complex digitaldesigns. Palnitkar offers a wealth of proven VerilogHDL modeling tips, and more than 300 fully-updatedillustrations, examples, and exercises. Each chaptercontains detailed learning objectives and convenientsummaries.

I. BASIC VERILOG TOPICS.
1. Overview of Digital Design with Verilog HDL.
2. Hierarchical Modeling Concepts.
3. Basic Concepts.
4. Modules and Ports.
5. Gate Level Modeling.
6. Data Flow Modeling.
7. Behavioral Modeling.
8. Tasks and Functions.
9. Useful Modeling Techniques.

II. ADVANCED VERILOG TOPICS.
10. Timing and Delays.
11. Switch Level Modeling.
12. User Defined Primitives
13. Programming Language Interface.
14. Logic Synthesis with Verilog HDL.

III. APPENDICES.
Appendix A. Strength Modeling and Advanced Net Definitions.
Appendix B. List of PLI Routines.
Appendix C. List of Keywords, System Tasks and Compiler
Directives.
Appendix D. Formal Syntax Definition.
Appendix E. Verilog Tidbits.
Appendix F. Verilog Examples.
Bibliography.