A Pipelined Multi-core Mips Machine ― Hardware Implementation and Correctness Proof
商品資訊
系列名：Lecture Notes in Computer Science / Theoretical
ISBN13：9783319139050
出版社：Springer-Verlag New York Inc
作者：Mikhail Kovalev; Silvia Melitta M?奸er; Wolfgang J. Paul
出版日：2014/12/01
裝訂：平裝
規格：22.9cm*15.2cm*1.9cm (高/寬/厚)
商品簡介
This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory.
The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory. This opens the way to the formal verification of synthesizable hardware for multi-core processors in the future.
Constructions are in a gate level hardware model and thus deterministic. In contrast the reference models against which correctness is shown are nondeterministic. The development of the additional machinery for these proofs and the correctness proof of the shared memory at the gate level are the main technical contributions of this work.
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